In the prior art it is known to improve the speed or throughput of a data processing system by the use of a relatively high speed, low capacity buffer store called a Cache memory to improve the apparent speed of the relatively low speed, high capacity Main memory or Main Storage Units (MSU). In the Vernon K. Anderson, et al, U.S. Pat. No. 3,967,247, there is disclosed such a system in which a Cache memory is incorporated within a Storage Interface Unit (SIU) that provides the means whereby a plurality of Requestors such as one or more Central Processing Units (CPUs) or Input/Output Units (IOUs) request and obtain access to data that is stored in one or more MSUs. In that system the R Requestors couple their separate Priority Request signals to a single Priority Network while all of the R Requestors couple their separate Requestor address (the address in the MSUs at which the requesting Requestor is seeking to read data from or write data into) to a single Cache memory. The Priority determination is made and then the address of the honored Requestor is gated into the Cache memory for the determination of a Match condition (the determination of whether, vel non, the honored Requestor address is resident in the Cache memory). This serial Priority determination, Match determination adds additional time to the memory access time such that the full, optimum use of the Cache memory system is not obtained. The present invention is directed toward an improvement of such prior art system.